Title :
Parallel computation of neural networks in a processor pipeline with partially shared memory
Author :
Okawa, Yoshikuni ; Suyama, Hiroyuki
Author_Institution :
Osaka Univ., Japan
Abstract :
A novel parallel architecture of a processor pipeline is proposed, comprising linearly connected processors via dual bank switchable memory blocks. A layered neural network with the back-propagating error algorithm is adopted as a benchmark test. The essential part of the algorithm is a matrix multiplication with a vector. An experimental system was implemented, and several measurements were made which demonstrate the suitability of the proposed architecture in some practical applications
Keywords :
artificial intelligence; learning systems; neural nets; parallel architectures; performance evaluation; back-propagating error algorithm; benchmark test; dual bank switchable memory blocks; linearly connected processors; matrix multiplication; neural networks; parallel architecture; parallel computation; partially shared memory; processor pipeline; Communication switching; Computer architecture; Computer networks; Concurrent computing; Intelligent networks; Neural networks; Parallel architectures; Parallel processing; Pipelines; Switches;
Conference_Titel :
Tools for Artificial Intelligence, 1990.,Proceedings of the 2nd International IEEE Conference on
Conference_Location :
Herndon, VA
Print_ISBN :
0-8186-2084-6
DOI :
10.1109/TAI.1990.130347
