Title :
Random pattern testability of memory control logic
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fDate :
27 Apr-1 May 1997
Abstract :
This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary
Keywords :
integrated memory circuits; logic testing; embedded memory control logic; exposure probability; fault detection; random pattern testability; signal probability; Computational modeling; Decoding; Fault detection; Feeds; Jacobian matrices; Logic testing; Pattern analysis; Predictive models; Random access memory; Read-write memory;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600317
