DocumentCode :
3053354
Title :
A reconfigurable macro-pipelined systolic accelerator architecture
Author :
Bao, Wenqi ; Jiang, Jiang ; Fu, Yuzhuo ; Sun, Qing
Author_Institution :
Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
fYear :
2011
fDate :
12-14 Dec. 2011
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, we propose a reconfigurable macro-pipelined systolic architecture (MAPS), which aims to accelerate multiply-accumulate based algorithms by exploiting the temporal parallelism. To illustrate the performance, we implement a 32-PE accelerator on the Xilinx ML605 experiment board for the matrix multiplication and get a peak performance of 51.2 GFLOPS (about 8.0 GFLOPS per PE per GHz). To demonstrate the generality for different algorithms, the 2-dimensional convolution is also implemented on the MAPS. Moreover, the proposed MAPS architecture has the excellent scalability, which is able to scale up to hundreds of GFLOPS using multiple FPGA devices.
Keywords :
field programmable gate arrays; matrix multiplication; parallel algorithms; pipeline processing; reconfigurable architectures; systolic arrays; 2-dimensional convolution; 32-PE accelerator; FPGA devices; GFLOPS; MAPS architecture; Xilinx ML605 experiment board; matrix multiplication; multiply accumulate based algorithm; reconflgurable macropipelined systolic accelerator architecture; scalability; temporal parallelism; Acceleration; Arrays; Bandwidth; Convolution; Copper; Indexes; Parallel processing; 2-dimensional convolution; accelerator architecture; macro-pipeline; matrix multiplication; systolic array;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2011 International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-1-4577-1741-3
Type :
conf
DOI :
10.1109/FPT.2011.6132702
Filename :
6132702
Link To Document :
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