Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips

The extensive use of Systems-on-Programmable-Chips (SoPCs) in many application domains emphasizes the importance of analysing the vulnerability of the designs to single-event upsets (SEUs) and proposing efficient low-cost mitigation approaches. Most SEU mitigation approaches proposed so far in the literature for SoPCs are based on the use of popular hardware redundant techniques combined with memory scrubbing to avoid fault accumulation. However, all these approaches do not exploit the fact that a large portion of the configuration bits for a particular mapped design are non-sensitive, i.e. do not affect the circuit behaviour in the presence of upsets. In this paper, we first analyse the sensitivity of the configuration bits of a SoPC mapped in a Xilinx Virtex-5 device relying on the vendor implementation tools. The sensitivity analysis showed that the configuration memory scrubbing “wastes” time scanning a large number of frames containing a disproportionately small number of configuration bits due to their high dispersion. To resolve this, we propose a constraint-driven re-placement method to reduce the number of sensitive configuration frames and consequently the scrubbing time. Finally, we present a low-cost SEU mitigation approach for SoPCs which uses configuration memory scan and scrubbing as fault detection and fault repair mechanisms combined with checkpointing and rollback for fault recovery. We demonstrate the efficiency of the proposed mitigation approach in a Leon3-based SoPC implemented in a Xilinx Virtex-5 device.