Design, Process Development and Prototyping of 3D Packaging with Multi-Stacked Flip Chips and Peripheral Through Silicon Via Interconnection

Three-dimensional packaging (3DP) is an emerging trend in microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. Prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs formed by deep reactive ions etching (DRIE) and TSVs plugging by copper plating for interconnection are studied and discussed in details. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this paper.