DocumentCode :
3053705
Title :
Statistical design of macro-models for RT-level power evaluation
Author :
Wu, Qing ; Ding, Chihshun ; Hsieh, Chengtah ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1997
fDate :
28-31 Jan 1997
Firstpage :
523
Lastpage :
528
Abstract :
This paper introduces the notion of cycle-accurate macro-models for RT-level power evaluation. These macro-models provide us with the capability to estimate the circuit power dissipation cycle by cycle at RT-level without the need to invoke low level simulations. The statistical framework allows us to compute the error interval for the predicted value from the user specified confidence level. The proposed macro-model generation strategy has been applied to a number of RT-level blocks and detailed results and comparisons are provided
Keywords :
high level synthesis; logic CAD; power consumption; RT-level power evaluation; circuit power dissipation; error interval; low level simulations; macro-models; statistical design; Capacitance; Circuit simulation; Clocks; Energy consumption; Equations; Frequency; Power dissipation; Power engineering and energy; Reactive power; Statistics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
Type :
conf
DOI :
10.1109/ASPDAC.1997.600325
Filename :
600325
Link To Document :
بازگشت