Electrical characterization and gate stack optimization of nitride trapping NVSM devices

A continued scaling of nonvolatile semiconductor memory (NVSM) devices has increased the appeal of nitride trapping memory devices over floating gate devices, since the former appear not to be limited by drain disturb effects or gate coupling issues. In this paper, we will present several techniques to electrically characterize and optimize the gate stack of nitride trapping NVSM devices. An automated flatband voltage tracking system has been developed to characterize the performance of NVSM capacitors and a model has been proposed to determine the vertical location of trapped charges in the nitride. In addition, we describe experiments on MANOS capacitors with varying silicon-rich and stoichiometric nitride stacks to study device performance.