Title :
Processor-Level Selective Replication
Author :
Nakka, Nithin ; Pattabiraman, Karthik ; Iyer, Ravishankar
Author_Institution :
Center for Reliable & High Performance Comput. Coordinated Sci. Lab., Urbana
Abstract :
We propose a processor-level technique called selective replication, by which the application can choose where in its application stream and to what degree it requires replication. Recent work on static analysis and fault-injection-based experiments on applications reveals that certain variables in the application are critical to its crash- and hang-free execution. If it can be ensured that only the computation of these variables is error-free, then a high degree of crash/hang coverage can be achieved at a low performance overhead to the application. The selective replication technique provides an ideal platform for validating this claim. The technique is compared against complete duplication as provided in current architecture-level techniques. The results show that with about 59% less overhead than full duplication, selective replication detects 97% of the data errors and 87% of the instruction errors that were covered by full duplication. It also reduces the detection of errors benign to the final outcome of the application by 17.8% as compared to full duplication.
Keywords :
error analysis; redundancy; application-aware; error detection; fault-injection; processor-level selective replication; redundant hardware; static analysis; Computer crashes; Computer networks; Detectors; Hardware; High performance computing; Instruction sets; Instruments; Prototypes; Redundancy; Safety; Application-aware; Critical Variable; Duplication.; Error Detection; Redundant Hardware;
Conference_Titel :
Dependable Systems and Networks, 2007. DSN '07. 37th Annual IEEE/IFIP International Conference on
Conference_Location :
Edinburgh
Print_ISBN :
0-7695-2855-4
DOI :
10.1109/DSN.2007.75