Title :
A hybrid NoC architecture utilizing packet transmission priority control method
Author :
Seungju Lee ; Togawa, N. ; Sekihara, Y. ; Aoki, Toyohiro ; Onozawa, A.
Author_Institution :
Dept. of Comput. Sci. & Eng., Waseda Univ., Tokyo, Japan
Abstract :
Network-on-chip architectures have emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). With the explosive growth in the usage of multimedia applications, it is expected that NoC serves as a multimedia server supporting multi-class services. Recently, a busmesh NoC (BMNoC) has been proposed. The BMNoC architecture, which analyses the data traffic and makes aware of localities between cores, improves the system performance in terms of latency as compared with conventional NoCs. In this paper, we propose a novel BMNoC utilizing packet transmission priority control methods. Our proposed BMNoC is a generalized and simplified version of a hybrid NoC which is composed of local buses and global mesh routers. Several realistic applications applied to our algorithm illustrate the better performance than previous studies and feasibility of our proposed architecture.
Keywords :
logic design; network-on-chip; system buses; BMNoC architecture; busmesh NoC; data traffic; global mesh routers; hybrid NoC architecture; local buses; multiclass services; multimedia applications; multimedia server; multiprocessor systems-on-chips; network-on-chip architectures; packet transmission priority control method; system performance; Communication networks; Computer architecture; Delay; Object detection; Ports (Computers); System-on-a-chip; Telecommunications;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6419057