A fast correlation based background digital calibration for pipelined ADCs

This paper presents a fast background digital calibration method for pipelined analog-to-digital converters (ADCs) that is robust and converges fast. To avoid the problem of input signal amplitude limitation, the proposed calibration technique takes advantage of the digital redundancy architecture by injecting pseudo-random noise (PN) in the sub-ADC. A split ADC architecture combined with a switch array control unit is also proposed to minimize the correlation between the input signal and the injecting PN signal. Simulation result shows, when the capacitor error is 0.1%, and the gain error between the two channel is 1%, the calibration time is about 2¹⁷ samples simulated with 15-bit accuracy with a 0.32/-0.33 LSB DNL and a 0.50/-0.24 LSB INL, and the SNDR is 91.5 dB, the SFDR is 110.3 dB.