Modeling of perimeter-gated silicon avalanche diodes fabricated in a standard single-well CMOS process

We investigate design, fabrication and numerical modeling details of a silicon impact ionization device that was implemented in a standard single-well CMOS process line for use in biomedical applications. Device performance modeling of the perimeter-gated silicon avalanche diode is presented. To lower dark current, tune the current multiplication rate, and change the breakdown voltage, two techniques were develop: First is laying out n-wells close to each other to favorably increase spatial aliasing of diffused dopants, and second is using a gate terminal at the perimeter to modify electric field in the vicinity of the p⁺-n junction. Results verified by calculations and simulations show that the device can be operated in photon-counter mode with high breakdown voltages and sharp current transitions or in current multiplication mode as in solid-state impact ionization multipliers.