Simulation of synchronous network-on-chip router for system-on-chip communication

System-on-chip communication is nowadays widely used communication technology. Continuous CMOS technology scaling makes it possible to integrate a large number of heterogeneous devices onto a single chip. Network-on-Chip (NoC), as a highly integrated heterogeneous System-on-Chip (SoC) architecture, presents the platform with the main demand to be reliable, cost and energy-efficient. This paper describes a simulation of 4×4 synchronous network-on-chip router for an efficient system-on-chip communication.