DocumentCode :
3062438
Title :
Interconnect technology for giga-scale integration
Author :
Liu, Ruichen ; Pai, Chien-Shing
Author_Institution :
Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
fYear :
1998
fDate :
1998
Firstpage :
17
Lastpage :
20
Abstract :
Key interconnect issues for giga-scale integration, interconnect architecture, delay and yield, are examined. Even using new materials. Cu and low K dielectric (K=2), interconnect delay still dominates and clock speed of 2 GHz for large circuits is not achievable without new innovation in architecture. Cumulative yield loss from multiple levels of interconnect will dominate the die yield, and the more promising reverse-scaling architecture suffers more severe yield loss due to increased die size. Overall, interconnect technology, at giga-scale integration will be one of the most challenging tasks and innovation in architecture is needed
Keywords :
ULSI; copper; integrated circuit interconnections; integrated circuit yield; nanotechnology; 100 nm; 2 GHz; Cu; clock speed; cumulative yield loss; delay; die size; die yield; giga-scale integration; interconnect architecture; interconnect delay; interconnect technology; low K dielectric; multiple levels; reverse-scaling architecture; yield; yield loss; Application specific integrated circuits; Clocks; Costs; Dielectric materials; Integrated circuit interconnections; Logic devices; Manufacturing; Microprocessor chips; Silicon; Technological innovation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-4306-9
Type :
conf
DOI :
10.1109/ICSICT.1998.785774
Filename :
785774
Link To Document :
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