A new architecture of digital clock synthesizers

A new architecture of digital clock synthesizers with an adjustable duty-cycle is designed, where two frequency control words (FCWs) are used to control the duration of each half cycle. In the architecture of the digital clock synthesizer, a set of reference inputs with the same frequency but different phases are first passed through a multiplexer (Mux), and the Mux will select the successive reference input to make its output achieve the maximum frequency. To eliminate the glitch from the Mux, an incrementer is used to control the Mux selection. The function and performance of the synthesizer are validated via implementation and simulations with the TSMC 0.18 mum cell-based library.