Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs

Author

Dutton, Bradley F. ; Stroud, Charles E.

Author_Institution

Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL

fYear

2009

fDate

15-17 March 2009

Firstpage

230

Lastpage

234

Abstract

A built-in self-test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 field programmable gate arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults in every CLB. There is no area overhead or performance penalty and the approach is applicable to all levels of FPGA testing (wafer, package, and in-system). A novel output response analyzer (ORA) design, which is efficiently implemented in FPGAs, provides both an overall single-bit pass/fail result and optimal diagnostic resolution when faults are detected. The implementation of the BIST approach in all Virtex-5 FPGAs and experimental results are discussed.

Keywords

built-in self test; fault diagnosis; field programmable gate arrays; logic testing; BIST approach; Virtex-5 FPGA testing; built-in self-test approach; configurable logic block; distributed RAM operation mode; field programmable gate array; output response analyzer design; stuck-at fault detection; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Field programmable gate arrays; Logic testing; Manufacturing; Programmable logic arrays; System testing; Built-In Self-Test; Field Programmable Gate Array; Virtex-5; configurable logic block;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 2009. SSST 2009. 41st Southeastern Symposium on

Conference_Location

Tullahoma, TN

ISSN

0094-2898

Print_ISBN

978-1-4244-3324-7

Electronic_ISBN

0094-2898

Type

conf

DOI

10.1109/SSST.2009.4806778

Filename

4806778