A VLSI design of a pipeline FFT in GF(256)

Author

Jinxiang, Wang ; Zhigang, Mao ; Yizheng, Ye

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

fYear

1998

fDate

23-23 Oct. 1998

Firstpage

373

Lastpage

376

Abstract

A pipeline VLSI design of FFT based on Good-Thomas algorithm is presented. To implement FFT with 255 points in GF(256), this design only needs 60 eight bits galois multipliers, a ROM to store 30 twiddles and some registers. The latency is 255+17 clock cycles, and the maximum combination delay is the sum of one multiplier in GF(256) and four stage XOR gates. This design is modular, regular, simple and suitable for VLSI implementation

Keywords

Galois fields; Reed-Solomon codes; VLSI; computational complexity; decoding; digital signal processing chips; discrete Fourier transforms; fast Fourier transforms; parallel algorithms; pipeline arithmetic; Good-Thomas algorithm; RS(255,223) decoder; VLSI design; VLSI implementation; four stage XOR gates; galois multipliers; maximum combination delay; modular design; one multiplier; pipeline FFT; transform decoding; twiddles storage ROM; Algorithm design and analysis; Clocks; Decoding; Delay; Discrete Fourier transforms; Equations; Galois fields; Pipelines; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing, China

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785899

Filename

785899