A simulator to train for finite state machine design

Author

Ponts, D. ; Donzellini, Giuliano

Author_Institution

Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy

Volume

2

fYear

1996

fDate

6-9 Nov 1996

Firstpage

725

Abstract

Presents a general-purpose simulator of finite state machines (FSM), developed for training purposes. Algorithms, represented graphically as algorithmic state machine charts, can be drawn directly on the computer screen, and directly tested in the state and time domains without the necessity for synthesizing the FSM logic circuits. The simulator facilitates the transition from the pedagogical level of digital design to the professional level, which is characterized by the use of CAD tools. It is currently being used in introductory digital electronics courses for several electronic engineering curricula

Keywords

circuit analysis computing; computer based training; diagrams; digital simulation; educational courses; electronic engineering education; engineering graphics; finite state machines; logic CAD; logic circuits; CAD tools; algorithmic state machine charts; digital design; electronic engineering curricula; finite state machine design; general-purpose simulator; graphical representation; introductory digital electronics courses; logic circuits; pedagogical level; professional level; state-domain testing; time-domain testing; training; Automata; Circuit simulation; Circuit testing; Computational modeling; Computer languages; Digital circuits; Digital systems; Education; Hardware design languages; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Frontiers in Education Conference, 1996. FIE '96. 26th Annual Conference., Proceedings of

Conference_Location

Salt Lake City, UT

ISSN

0190-5848

Print_ISBN

0-7803-3348-9

Type

conf

DOI

10.1109/FIE.1996.573055

Filename

573055