A multi-signal bus architecture for FIR filters with single bit coefficients

An architecture for FIR filter with binary coefficients based on partitioning the filter transfer function is investigated. Two computational complexity measures, corresponding to VLSI implementation and to the number of adders are minimized with respect to a partition parameter. One of the optimal architectures is shown to require adders instead of . This is attributed to the fact that the proposed architecture removes, in an optimal fashion, redundancies shown to inherently exist in the filter structure. This is achieved by precomputing from the input signal other signals that are most commonly needed through the filter structure in what might be called a multisignal bus architecture.