Title :
A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond
Author :
Sato, H. ; Yamagata, T. ; Fujita, K. ; Nisimura, Y. ; Anami, K.
Author_Institution :
LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A Distributed Globally Replaceable Redundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.
Keywords :
DRAM chips; MOS integrated circuits; SRAM chips; VLSI; redundancy; 0.5 micron; distributed globally replaceable redundancy scheme; dynamic RAM; static RAM; sub-half micron ULSI memories; yield simulator; DRAM chips; MOS integrated circuits, memory; Redundancy; SRAM chips; Ultra-large-scale integration; Yield optimization;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920561
