A 1.5 ns cycle-time 18 kb pseudo-dual-port RAM

Author

Usami, M. ; Iwabuchi, M. ; Kashiyama, M. ; Oomori, T. ; Murata, S. ; Hiramoto, T. ; Hashimoto, T. ; Nakajima, Y.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

109

Lastpage

110

Abstract

High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.

Keywords

bipolar integrated circuits; integrated memory circuits; large scale integration; random-access storage; semiconductor-insulator boundaries; silicon; 1.5 ns; 18 kbit; SOI wafer; Si; double polysilicon self-aligned bipolar process; high-speed memories; peripheral logic gates; pseudo-dual-port RAM; trench isolation; Bipolar integrated circuits, memory; High-speed integrated circuits; Large-scale integration; Logic-in-memory; Random-access memories; Silicon-on-insulator;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920565

Filename

920565