A novel single-rail variable encoded completion detection scheme for self-timed circuit design using ternary multiple valued logic

The performance and success of many self-timed design methodologies commonly rely heavily on completion detection schemes in order to reliably acknowledge the termination of a computation associated with a self-timed functional block. A particularly vexing problem associated with many self-timed completion detection schemes proposed in the literature, is the task of implementing the robust and successful generation of a completion done signal, denoting the termination of a self-timed event, on every computation handled by a self-timed functional block. Many research groups who have focused on the development of asynchronous self-timed design methodologies have proposed methods to successfully detect the completion of a self-timed computation. However, a universally acceptable solution that successfully detects the completion of a self-timed event on every cycle of computation for an arbitrary self-timed functional block, remains to this day, an elusive technical issue. A specific case, related to data conditioning, that proves to be fundamentally problematic in many self-timed completion detection schemes that have been proposed, involves the successful generation of a self-timed components´ completion detection signal on consecutive cycles of computation. This is equivalent to cases where the nature of the input data is such that the resulting output generated on subsequent computational cycles is the same as the previous cycles´ result (“same state similarity”). In this paper, the authors´ propose a novel approach to completion detection, for use in asynchronous self-timed designs, that employs a ternary multiple valued logic (“MVL”) approach using dynamic CMOS circuit design techniques, that guarantees the failproof generation of event termination on every self-timed computational cycle, including cases of same state similarity