Title :
Design framework for systolic-type arrays
Author :
Jover, Juan-Manuel ; Kailath, Thomas
Author_Institution :
Stanford University, Stanford, CA
Abstract :
We present a framework for the design and description of Systolic-type Arrays. The framework is based on the definition of a conceptual tool, Lines of Computation (LOC´s) that allows us to systematically define a generalization of the idea of Systolic Arrays and Wavefront Array Processors. We use three different architectures for parallel matrix multiplication to show the power of LOC´s to describe and generate Systolic-type Arrays. Finally, we present some topographical properties of Systolic Arrays that can be readily analyzed using LOC´s ideas.
Keywords :
Computer architecture; Design methodology; Information systems; Inspection; Lab-on-a-chip; Laboratories; Power generation; Systolic arrays; Topology; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '84.
DOI :
10.1109/ICASSP.1984.1172408