• DocumentCode
    3073002
  • Title

    Modelling a CNTFET with Undeposited CNT Defects

  • Author

    Cho, Geunho ; Lombardi, Fabrizio ; Kim, Yong-Bin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
  • fYear
    2010
  • fDate
    6-8 Oct. 2010
  • Firstpage
    289
  • Lastpage
    296
  • Abstract
    The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When designing and manufacturing a CNTFET, additional features such as pitch, number and position of the CNTs must be considered to assess its performance. One of the defect types that can occur when fabricating a CNTFET, is the absence of some CNTs following the deposition/growth step. As result of this type of defect, a CNTFET will show a change in operational characteristics because drain current, gate capacitance, and delay will be affected due to the lower number of CNTs present in the channel of the transistor. This paper presents a new model by which the drain current, the gate capacitance and the delay can be found when not all CNTs are deposited on the substrate. This results in an uneven CNT spacing, new equations are derived and shown to be applicable to both defective and defect-free CNTFETs. The proposed model has been implemented in MATLAB and has been extensively simulated to show that defects due to undeposited CNTs have a significant impact on the operation of a CNTFET. Degradation in performance is related to both the number and position of the defects.
  • Keywords
    carbon nanotubes; field effect transistors; nanoelectronics; C; CNT spacing; CNTFET; MATLAB; carbon nanotube field effect transistor; delay; drain current; gate capacitance; undeposited CNT defects; CNTFETs; Capacitance; Equations; Logic gates; MOSFET circuits; Mathematical model; Substrates; CNT; CNTFET; Defect model; emerging technologies; manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
  • Conference_Location
    Kyoto
  • ISSN
    1550-5774
  • Print_ISBN
    978-1-4244-8447-8
  • Type

    conf

  • DOI
    10.1109/DFT.2010.42
  • Filename
    5634914