A family of custom VLSI circuits for speech recognition

The design of a custom VLSI circuit that has the potential of achieving a high throughput when executing one of the most computationally expensive modules of a speech recognition system is presented. The architecture of the device is described in terms, of a set of self-timed building blocks that implement arithmetic operations, storage and input/output functions. The formalism used to describe the architecture makes it easy to define variations of the basic structure in order to deal with recognition systems that use different heuristics and search different kinds of databases. A tool that helps the designer investigate the area/speed trade-offs is also described.