DocumentCode
3073183
Title
Statistical circuit characterization for deep-submicron CMOS designs
Author
Chen, J. ; Orshansky, M. ; Chenming Hu ; Wan, C.-P.
Author_Institution
California Univ., Berkeley, CA, USA
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
90
Lastpage
91
Abstract
Aggressive scaling of CMOS MOSFET gate lengths is halving minimum device channel lengths every 4 to 6 years. This brings an increase in deep-submicron device performance sensitivity to manufacturing variations. Its impact on highly-integrated, system-on-a-chip designs needs assessment to ensure first-pass silicon and adequate yield.
Keywords
CMOS digital integrated circuits; MOSFET; SPICE; VLSI; digital simulation; integrated circuit yield; statistical analysis; MOSFET gate lengths; deep-submicron CMOS designs; deep-submicron device performance sensitivity; first-pass silicon; manufacturing variations; minimum device channel lengths; statistical circuit characterization; system-on-a-chip designs; yield; Analytical models; CMOS logic circuits; Circuit optimization; Principal component analysis; Ring oscillators; SPICE; Semiconductor device modeling; Stochastic systems; Threshold voltage; Velocity measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672388
Filename
672388
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