• DocumentCode
    3073253
  • Title

    Reliability assessments and designs for fine pitch flip chip packages with Cu column bumps

  • Author

    Ming-Che Hsieh ; Chien Chen Lee ; Li Chiun Hung

  • Author_Institution
    STATS ChipPAC Taiwan Co. Ltd., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    24-26 Oct. 2012
  • Firstpage
    280
  • Lastpage
    283
  • Abstract
    Because the utilization of copper column bump (with lead-free solder cap) interconnects performs the characteristic of fine pitch bump in flip chip technology (less than 150um bump pitch), supplies the flexibility of Cu column aspect ratio and efficiently increases the I/O density, lots of researches for Cu column bumps in flip chip packages are widely investigated. For the purpose of realizing the mechanical behaviors for fcFBGA (flip chip fine pitch BGA) with Cu column bumps, the three-dimensional finite element analysis (FEA) modeling has been used to obtain their warpage and stress responses. The reliability assessment for underfill selection is presented to validate the FEA results. Since the packaging geometry and material always plays the important role to affect mechanical behaviors, having the overall discussions to capture the critical factors that impact the stresses and warpage responses are useful to reduce the stress and warpage in fcFBGA. In order to gain the essential factors in fcFBGA, the systematic simulation studies for Cu column bumps are illustrated. The impact levels for top significant factors to influence the extreme low-k (ELK), under-bump-metallurgy (UBM) and bump stresses as well as the warpage are presented. The proposed results will be helpful not only for reducing warpage but also for keeping off the critical stresses in fcFBGA with Cu column bumps. It is believed that these results will be the design guidelines to enhance the package reliability and reduce the package costs during the development stage.
  • Keywords
    finite element analysis; flip-chip devices; integrated circuit reliability; I/O density; bump stresses; copper column bump; extreme low-k; fine pitch bump; fine pitch flip chip packages; lead-free solder cap interconnects; mechanical behaviors; package costs; package reliability; reliability assessments; stress response; systematic simulation studies; three-dimensional finite element analysis; under-bump-metallurgy; utilization; warpage response; Electromagnetic compatibility; Flip chip; Packaging; Reliability; Stress; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 7th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4673-1635-4
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2012.6420243
  • Filename
    6420243