Survey of oxide degradation in inverter circuits using 2.0 nm MOS devices

Degradation in CMOS inverter circuit performance as a result of gate oxide wearout in 2.0 nm pMOSFETs was investigated using a constant voltage stress (CVS) technique. It is demonstrated that inverter performance in the time-domain shows significant deterioration when only the pMOSFET experiences wearout. Experimental results indicate loss of inverter circuit performance in the time-domain given by approximately 36% to 62% increase in the rise time. Conversely, DC inverter characteristics are potentially misleading showing that inverter performance was only partially altered. In both cases, inverter degradation is related to the pMOSFET suffering as much as a 40% decrease in drive current after wearout. This and other large changes in device parameters are compared to a typical logic process revealing that the device parameters are outside the process window. Ultimately, this study suggests that wearout in ultra-thin gate oxides may lead to increased circuit degradation despite the gate leakage current associated with a known circuit component being lower than that required for a typical or traditional BD event to occur.