A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields

Concurrent error detection (CED) schemes for finite field multipliers over GF(2^m), based on simple parity bits, have been proposed in the literature. In this paper, we generalize the concept of parity and derive a hybrid scheme for CED. We extend the one-bit parity concept to multiple parity based on generalized (mod g(x)) reduction. Then, we combine this concept together with N-fold redundant reduction modules and apply this to finite field multipliers. The proposed scheme is faster and smaller than simple-parity-bit schemes and provides the same or better error detection capability. For example, implemented on FPGA for 20 parity bits over GF(2¹⁶³), the overhead and output delay of the hybrid scheme are 7% and 39 nS, while those of the parity protected scheme are 80% and 198 nS, respectively.