• DocumentCode
    3073571
  • Title

    Design and implementation of ultra-thin SiP modules

  • Author

    Meng-Sheng Chen ; Yung-Chung Chang ; Wei-Ting Chen ; Tzu-Ying Kuo ; Li-Chi Chang ; Cheng-Hua Tsai ; Chang-Chih Liu ; Chang-Sheng Chen ; Cheng-Ta Ko ; Yung-Yu Wang ; Long-Zhen Liang

  • Author_Institution
    Electron. & Opto-Electron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    24-26 Oct. 2012
  • Firstpage
    311
  • Lastpage
    314
  • Abstract
    In recent years, SiP (System-in-Package) or SOP (System on Package) technology has become an attractive solution for size reduction of mobile devices. Passive components such as inductors or capacitors can be integrated into the substrate. The dimension of embedded capacitors can be further reduced by using high dielectric constant material. Thus, size miniaturization and cost reduction can be easily achieved through the replacements of surface-mounted devices (SMDs) on the substrate.chip can be reduced. Wafer-level packaging technology, wafer thinning technology, buried ultra-thin chips technology, and embedded passive components technology are both integrated in this paper to achieve a miniaturized ultra-thin SiP module. The feasibility of the ultra-thin SiP technology was verified by using a GPS module. For high integration and flexible design, an eight-layered organic substrate process is used in this project.
  • Keywords
    capacitors; multichip modules; permittivity; surface mount technology; system-in-package; system-on-package; wafer level packaging; GPS module; SMD; SOP technology; buried ultra-thin chips technology; cost reduction; dielectric constant material; eight-layered organic substrate process; embedded capacitors; embedded passive components technology; miniaturized ultra-thin SiP module; mobile devices; size miniaturization; size reduction; surface-mounted devices; system on package technology; system-in-package technology; ultra-thin SiP modules; wafer thinning technology; wafer-level packaging technology; Capacitors; Electric shock; Flip chip; Global Positioning System; Substrates; Surface treatment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 7th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4673-1635-4
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2012.6420260
  • Filename
    6420260