• DocumentCode
    3073980
  • Title

    An Analytical Error Model for Pattern Clipping in DNA Self-Assembly

  • Author

    Arani, Zahra Mashreghian ; Hashempour, Masoud ; Lombardi, Fabrizio

  • Author_Institution
    Dept. of ECE, Northeastern Univ., Boston, MA, USA
  • fYear
    2010
  • fDate
    6-8 Oct. 2010
  • Firstpage
    7
  • Lastpage
    15
  • Abstract
    Large and complex structures commonly referred to as patterns can be generated using DNA-like self-assembly. Self-assembly has an algorithmic nature, that is suitable for diverse applications in nano computing and manufacturing. This paper deals with the error characterization and modeling encountered when only a partial pattern is grown by DNA self-assembly. Partial growth is accomplished by clipping and utilizing specific structures (such as rulers, decoders and staircases) to allow the control of the growth process, i.e. the self-assembly can be either stopped or redirected as required. Initially the characterization of tile errors that are possible when clipping a pattern (such as the Sierpinski Triangle pattern), is presented with particular emphasis on the effects of erroneous aggregation in the capabilities of the clipping structures. An analytical approach is proposed to assess the effects of errors on clipping, this approach utilizes a geometric technique by which growth can be assessed with respect to the features of the desired (clipped) pattern. Simulation results are also presented, an excellent agreement between simulated and analytical results is achieved.
  • Keywords
    DNA; error analysis; molecular biophysics; nanofabrication; self-assembly; DNA self-assembly; algorithmic nature; analytical approach; analytical error model; clipping structure; diverse application; error characterization; nanocomputing; nanomanufacturing; partial growth; partial pattern; pattern clipping; Assembly; DNA; Decoding; Process control; Self-assembly; Tiles; DNA self-assembly; algorithmic assembly; error analysis; error tolerance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
  • Conference_Location
    Kyoto
  • ISSN
    1550-5774
  • Print_ISBN
    978-1-4244-8447-8
  • Type

    conf

  • DOI
    10.1109/DFT.2010.8
  • Filename
    5634975