• DocumentCode
    3074760
  • Title

    A high precision 1024-point FFT processor for 2D convolution

  • Author

    Wosnitza, M. ; Cavadini, M. ; Thaler, M. ; Troster, G.

  • Author_Institution
    Electron. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland
  • fYear
    1998
  • fDate
    5-7 Feb. 1998
  • Firstpage
    118
  • Lastpage
    119
  • Abstract
    A chip for real-time computation of 256-, 512- and 1024-point Fourier-transforms uses architecture targeting frequency-domain convolution of real-valued 1024/spl times/1024 data-sets at 5 Frames/s. Compared to existing FFT-designs, the processor also supports element-wise matrix multiplication (MUL) and dedicated pre- and post-processing steps required for simultaneous transformation of two real-valued sequences with one complex FFT (cf. real-valued FFT). In addition, considering the large dynamic numerical range required for 2D frequency-domain convolution, the ALU-arithmetic is based on twos complement data-sets represented with 64b (2/spl times/32) complex mantissa and an additional 8b exponent. Under nominal conditions of 20/spl deg/C room temperature and 3.3 V power supply, the ALU computes a complex 1024-pt FFT within 80 /spl mu/s.
  • Keywords
    convolution; digital arithmetic; digital signal processing chips; fast Fourier transforms; frequency-domain analysis; 20 degC; 2D convolution; 3.3 V; 64 bit; 80 mus; ALU-arithmetic; FFT processor; dynamic numerical range; element-wise matrix multiplication; frequency-domain convolution; post-processing steps; real-time computation; real-valued sequences; twos complement data-sets; Convolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-4344-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.1998.672398
  • Filename
    672398