A Self Learning VLSI Lab along with Web-Based Platform to Design Schematics and Layouts

We present a web-based environment along with an interactive interface for VLSI schematic design, simulation, and layout design. It consist of 10 experiments starting from transistor level design of inverter, then some basic gates such as NAND, NOR, XOR etc, finally design of D latch and flip flop. In each experiment student will learn how to design VLSI circuits both schematic and layout. It also consists of experiment components such as objective, introduction, quiz, and theory etc. which gives step by step explanation of each experiment. It is a powerful self learning supplement for the VLSI design course offered in undergraduate engineering program. Along with teaching schematics and layouts of circuits, this virtual lab also consists of some experiment explaining about SPICE coding, VHDL and Verilog coding. An interactive panel is given in which student will write programming codes, simulate and see real time waveforms. The web based schematic and layout editor is designed to maintain the commonality with EDA tools such as Cadence Virtuoso, HSpice Cosmos, Tanner tools etc.