DocumentCode :
3075085
Title :
Multi-ASIP platform synthesis for real-time applications
Author :
Micconi, Laura ; Gangadharan, Deepak ; Pop, Paul ; Madsen, J.
Author_Institution :
Tech. Univ. of Denmark, Lyngby, Denmark
fYear :
2013
fDate :
19-21 June 2013
Firstpage :
59
Lastpage :
67
Abstract :
In this paper we are interested in deriving a distributed platform, composed of heterogeneous processing elements, targeted to applications that have strict timing constraints. We consider that the platform may use multiple Application Specific Instruction Set Processors (ASIPs). An ASIP is synthesized and tuned for a specific set of tasks (i.e., a task cluster). During design space exploration (DSE), we evaluate each platform solution visited in terms of its cost and performance, i.e., its ability to execute the applications such that they meet their timing constraints. To determine if the applications are schedulable, we have to know the worst-case execution time (WCET) of each task. However, we can determine the WCETs only after the ASIPs are synthesized, which is time consuming and therefore cannot be done during DSE. To address this circular dependency (the ASIPs depend on the task clustering, and the WCETs of tasks, used to determine schedulability, depend on how ASIPs are synthesized), we propose an uncertainty model for the WCETs, which captures the range of possible ASIP implementations. Based on this model, we synthesize a multi-ASIP platform, such that the applications have a high chance of being schedulable and the cost constraints imposed on the platform are fulfilled. We propose an Evolutionary Algorithm-based approach, which uses a novel stochastic schedulability analysis to solve this optimization problem. The proposed approach has been evaluated using several benchmarks.
Keywords :
distributed processing; evolutionary computation; multiprocessing systems; scheduling; DSE; WCET; application specific instruction set processors; design space exploration; distributed platform; evolutionary algorithm; heterogeneous processing element; multiASIP platform synthesis; optimization problem; stochastic schedulability analysis; timing constraint; worst-case execution time; Decoding; Digital audio players; Microarchitecture; Program processors; Radio frequency; Uncertainty; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Embedded Systems (SIES), 2013 8th IEEE International Symposium on
Conference_Location :
Porto
Type :
conf
DOI :
10.1109/SIES.2013.6601471
Filename :
6601471
Link To Document :
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