A New Parallel Algorithm for Analog Circuit Simulation

Parallel simulation is an efficient strategy to accelerate the simulation process for the analog circuit designs with increasing size. In this paper, low communication and coarse grain parallelization are concerned to achieve good performance on network of workstations. First, to split differential/algebraic system presenting the electronic circuit into sub-blocks, we present an efficient partitioning technique to produce sub-blocks with few interconnections. Second, for minimizing communication between the partitions, a set of evaluation factors are defined and a new static load balancing algorithm is proposed. At last, a practical circuit is taken to demonstrate the speedup of the parallel algorithm.