A 400 M sample/s 6b CMOS folding and interpolating ADC

A 6b 400 MSample/s folding and interpolating CMOS ADC uses a low-impedance current-mode approach. Current division interpolation in the folders allows fast low-voltage operation. This interpolation together with a short aperture comparator, gives good performance for high-frequency inputs, without using a sample-and-hold. The ADC uses a single clock and its complement. The 0.6 mm/sup 2/ CMOS converter, fabricated in a 0.5 /spl mu/m BiCMOS process dissipates 200 mW from a 3.2 V supply.