FPGA implementation of FFT processor using vedic algorithm

Fast Fourier Transform is an essential data processing technique in communication systems and DSP systems. In this brief, we propose high speed and area efficient 64 point FFT processor using Vedic algorithm. To reduce computational complexity and area, we develop FFT architecture by devising a radix-4 algorithm and optimizing the realization by Vedic algorithm. Furthermore, it can be used in decimation in frequency (DIF) and decimation in time (DIT) decompositions. Moreover, the design can achieve very high speed, which makes them suitable for the most demanding applications of FFT. Indeed, the proposed radix-4 Vedic algorithm based architecture requires fewer hardware resources. The synthesis results are same as that of theoretical analysis and it is observed that more than 15% reduction can be achieved in terms of slices count. In addition, the dynamic power consumption can be reduced and speed can be increased by as much as 16% using Vedic algorithm.