Author :
Griffin, M. ; Zerbe, J. ; Chan, A. ; Jun, Y.-H. ; Tanaka, Y. ; Richardson, W. ; Tsang, G. ; Ching, M. ; Portmann, C. ; Li, Y.-X. ; Stonecypher, B. ; Lai, L. ; Lee, K.H. ; Lee, V. ; Stark, D. ; Modarres, H. ; Batra, P. ; Louis-Chandran, J. ; Privitera, J.
Author_Institution :
Rambus Inc., Mountain View, CA, USA
Abstract :
A third-generation Rambus DRAM device is described which attains greater than 800 MB/s concurrent performance while performing all 260,000 test vectors using a design ported across multiple DRAM vendors.
Keywords :
DRAM chips; 800 MB/s; DRAM; bytewide interface; command interleaving; concurrent memory operation; concurrent performance; multiple DRAM vendors; test vectors; third-generation Rambus; Bandwidth; Capacitance; Circuit noise; Clocks; Decoding; Interleaved codes; MOS devices; Phase noise; Random access memory; Variable structure systems;
