A design for test perspective on I/O management

The widespread adoption of hardware description languages (HDLs) and structured design for testability (DFT) methods in ASIC design flows has led to an increasing emphasis on technology independence. Many DFT techniques such as boundary scan design, I/O sharing between test and functional ports. I/O wrap testing etc., rely on an accurate I/O specification. This paper describes some novel technology independent solutions to the problem of I/O cell specification and synthesis of DFT structures that involve I/O cell transformations. The solution speed up behavioral simulation of the HDL specification while also providing accurate I/O models for test synthesis