DocumentCode :
3079788
Title :
A VLSI array architecture with dynamic frequency clocking
Author :
Ranganathan, N. ; Vijaykrishnan, N. ; Bhavanishankar, N.
Author_Institution :
Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
fYear :
1996
fDate :
7-9 Oct 1996
Firstpage :
137
Lastpage :
140
Abstract :
In this paper, we describe the concept of dynamic frequency clocking and the design of a linear VLSI array processor, DFLAP, for use in image processing applications. Dynamic frequency clocking enables the chip to operate at different frequencies switching dynamically depending on the instruction being executed. Such a technique facilitates better management of throughput and power requirements in a VLSI system. The applicability of dynamic clocking in pipelined systems is also investigated. The effectiveness of the dynamic frequency architecture is illustrated by mapping several tasks for image processing applications
Keywords :
VLSI; image processing; parallel architectures; DFLAP; VLSI array architecture; dynamic frequency clocking; image processing; linear VLSI array processor; power requirements; throughput; Clocks; Computer architecture; Frequency conversion; Frequency synthesizers; Image processing; Logic; Reconfigurable architectures; Signal generators; Switching circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-7554-3
Type :
conf
DOI :
10.1109/ICCD.1996.563547
Filename :
563547
Link To Document :
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