Title :
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks
Author :
Al-Dujaily, Ra´ed ; Mak, Terrence ; Xia, Fei ; Yakovlev, Alex ; Palesi, Maurizio
Author_Institution :
Sch. of Electr., Electron. & Comput. Eng., Newcastle Univ., Newcastle-upon-Tyne, UK
Abstract :
Interconnection networks with adaptive routing are susceptible to deadlock, which could lead to performance degradation or system failure. Detecting deadlocks at run-time is challenging because of their highly distributed characteristics. In this paper, we present a deadlock detection method that utilizes run-time Transitive Closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in networks-on-chip (NoC). This detection scheme guarantees the discovery of all true deadlocks without false alarms unlike state-of-the-art approximation and heuristic approaches. A distributed TC-network architecture which couples with the NoC architecture is also presented to realize the detection mechanism efficiently. Our results based on a cycle-accurate simulator demonstrate the effectiveness of the TC-network method. It drastically outperforms timing-based deadlock detection mechanisms by eliminating false detections and thus reducing energy dissipation in various traffic scenarios. For example, timing based methods may produce two orders of magnitude more deadlock alarms than the TC-network method. Moreover, the implementations presented in this paper demonstrate that the hardware overhead of TC-networks is insignificant.
Keywords :
integrated circuit interconnections; network routing; network-on-chip; NoC architecture; adaptive routing; coupled transitive closure networks; cycle-accurate simulator; deadlock-equivalence sets; distributed TC-network architecture; heuristic approaches; interconnection network; network-on-chip; performance degradation; run-time TC computation; run-time deadlock detection; run-time transitive closure computation; state-of-the-art approximation; system failure; timing-based deadlock detection mechanisms; Clocks; Computer architecture; Hardware; Routing; Silicon; System recovery; System-on-a-chip;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
Print_ISBN :
978-1-61284-208-0
DOI :
10.1109/DATE.2011.5763086