Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

Gate sizing and threshold voltage selection is an important step in the VLSI physical design process to help reduce power consumption and improve circuit performance. Recent asynchronous design flows try to directly leverage synchronous EDA tools to select gates, which have a lot of limitations due to the intrinsic difference between asynchronous and synchronous circuits. This paper presents a new simultaneous gate sizing and Vth assignment approach for asynchronous designs. We formulate the asynchronous gate version selection problem considering both leakage power consumption and cycle time. Then, the optimization is performed based on a Lagrangian relaxation framework. A fast and effective slew updating strategy is also proposed to address the timing-loops of asynchronous circuits during static timing analysis. Our approach is evaluated using a set of asynchronous designs based on the pre-charged half buffer (PCHB) template and compared with the Proteus asynchronous design flow which is leveraging synchronous EDA tools. The experiments show our approach can achieve much better quality results in terms of both leakage power and cycle time compared with the other approach.