Modeling the technology impact on the design of a two-level multicomputer interconnection network

Author

Cruz-Rivera, José L. ; Wills, Scott ; Gaylord, Thomas ; Glytsis, Elias

Author_Institution

Dept. of Electr. & Comput. Eng., Puerto Rico Univ., Mayaguez, Puerto Rico

fYear

1996

fDate

7-9 Oct 1996

Firstpage

165

Lastpage

169

Abstract

The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for intrachip and interchip communication. An analysis of the impact several architectural and technological parameters have on the optimal network implementation (based on average no-load latency) is presented

Keywords

multichip modules; multiprocessor interconnection networks; parallel architectures; 4,096 node processing system; MCM substrate; VLSI; interchip; interconnection networks; intrachip; k-ary n-cube networks; multicomputer interconnection network; packaging; technology impact; two-level interconnect; Computer architecture; Concurrent computing; Delay; Multiprocessor interconnection networks; Packaging; Portable computers; Space technology; Substrates; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7554-3

Type

conf

DOI

10.1109/ICCD.1996.563553

Filename

563553