Title :
Suppression of anti-resonance peaks by controlling off-chip damping parameters
Author :
Iijima, Y. ; Sudo, Toshio ; Kinoshita, T. ; Uriu, Kazuhide
Author_Institution :
Shibaura Inst. of Technol., Tokyo, Japan
Abstract :
Simultaneous switching noise (SSN) is a serious design issue to stabilize power supply integrity and logic operation in advanced CMOS circuits and systems. Furthermore, SSN causes electromagnetic interference (EMI). Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of the total PDN impedance. Therefore, suppressing the anti-resonance peak is currently one of the most important design concerns in VLSI systems. In this paper, the method which is called “on-board snubber circuits (RC series circuits)” has been studied to suppress the anti-resonance peak. The on-board snubber circuits was added just at the beneath of the power supply terminals of the LSI to effectively suppress the anti-resonance peak of the total PDN impedance. In particular, the design space for damping the anti-resonance peak critically and the added values of capacitance (Csnb) and resistance (Rdmp) of the snubber circuits has been examined.
Keywords :
CMOS integrated circuits; RC circuits; VLSI; electromagnetic interference; interference suppression; snubbers; EMI; LSI; RC series circuits; SSN waveforms; VLSI systems; advanced CMOS circuits; antiresonance peak frequency suppression; electromagnetic interference; logic operation; off-chip damping parameter control; on-board snubber circuits; power supply integrity stability; power supply terminals; ringing frequency; simultaneous switching noise; total PDN impedance; Capacitance; Capacitors; Damping; Impedance; Integrated circuit modeling; Power supplies; Snubbers;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE
Conference_Location :
Nara
Print_ISBN :
978-1-4799-2313-7
DOI :
10.1109/EDAPS.2013.6724397
