Title :
Branch-directed and stride-based data cache prefetching
Author :
Liu, Yue ; Kaeli, David R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
Cache memories are commonly used to reduce the performance gap between microprocessor and memory technology. To increase the chances that a cache can provide instructions and data when requested, prefetching can be employed. Prefetching attempts to prime the cache with instructions and data which will be accessed in the near future. The work presented describes a prefetching algorithm which ties data cache prefetching to branches in the instruction stream. History of the data references is incorporated into a branch target buffer (BTB). Since branch instructions determine which instruction path is followed data access patterns are also dependent upon branch behavior. Results indicate that combining this strategy with tagged prefetching can significantly improve cache hit ratios. While improving cache hit rates is important, our prefetching policy significantly reduces the overall memory bus traffic
Keywords :
cache storage; memory architecture; microprocessor chips; microprogramming; performance evaluation; program control structures; branch instructions; branch target buffer; branch-directed prefetching; cache memories; data access patterns; data references; instruction stream; memory bus traffic; microprocessor technology; prefetching policy; stride-based data cache prefetching; tagged prefetching; Accuracy; Bridges; Cache memory; Delay; Frequency; Hardware; History; Microprocessors; Pipelines; Prefetching;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563561