• DocumentCode
    3082826
  • Title

    An efficient algorithm for multi-domain clock skew scheduling

  • Author

    Zhi, Yanling ; Luk, Wai-Shing ; Zhou, Hai ; Yan, Changhao ; Zhu, Hengliang ; Zeng, Xuan

  • Author_Institution
    Microelectron. Dept., Fudan Univ., Shanghai, China
  • fYear
    2011
  • fDate
    14-18 March 2011
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Conventional clock skew scheduling for sequential circuits can be formulated as a minimum cycle ratio (MCR) problem, and hence can be solved effectively by methods such as Howard´s algorithm. However, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for the flip-flops. Multi-domain clock skew scheduling was proposed to tackle this impracticality by constraining the total number of clock delays. Even though this problem can be formulated as a mixed integer linear programming (MILP), it is expensive to solve optimally in general. In this paper, we show that, under mild restrictions, the underlying domain assignment problem can be formulated as a special MILP that can be solved effectively using similar techniques for the MCR problem. In particular, we design a generalized Howard´s algorithm for solving this problem efficiently. We also develop a critical-cycle-oriented refinement algorithm to further improve the results. The experimental results on ISCAS89 benchmarks show both the accuracy and efficiency of our algorithm. For example, only 4.3% of the tests have larger than 1% degradation (3% in the worst case), and all the tests finish in less than 0.7 seconds on a laptop with a 2.1GHz processor.
  • Keywords
    clocks; flip-flops; integer programming; linear programming; logic design; scheduling; sequential circuits; arbitrary dedicated clock delays; critical-cycle-oriented refinement algorithm; domain assignment problem; flip-flops; generalized Howard´s algorithm; minimum cycle ratio problem; mixed integer linear programming; multidomain clock skew scheduling; sequential circuits; Algorithm design and analysis; Clocks; Clustering algorithms; Degradation; Scheduling; Sequential circuits; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
  • Conference_Location
    Grenoble
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-61284-208-0
  • Type

    conf

  • DOI
    10.1109/DATE.2011.5763220
  • Filename
    5763220