Fast-settling CMOS operational amplifiers with negative conductance voltage gain enhancement

Author

Yan, Jie ; Geiger, Randall L.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

228

Abstract

Negative conductance voltage gain enhancement techniques which substantially increases the DC gain of an operational amplifier without degrading speed are discussed. Three fully differential CMOS op amps using the negative conductance gain enhancement technique are presented. Simulations show that for a 0.35 μm CMOS technology with a power supply of 3 V, a DC gain of more than 94 dB is achievable with the proposed amplifiers. Settling measurements with a feedback factor of β=½ show fast settling behavior and a settling accuracy of better than 0.1% for a 1.2 V input step

Keywords

CMOS analogue integrated circuits; differential amplifiers; negative resistance circuits; operational amplifiers; 0.35 micron; 3 V; 94 dB; CMOS operational amplifiers; DC gain improvement; fast-settling CMOS opamps; fully differential CMOS op amps; negative conductance voltage gain enhancement; CMOS technology; Degradation; Equivalent circuits; Frequency; Impedance; Low voltage; Operational amplifiers; Power dissipation; Power supplies; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921832

Filename

921832