DocumentCode
3083072
Title
A syndrome-based LDPC decoder with very low error floor
Author
Tsatsaragkos, I. ; Kanistras, N. ; Paliouras, V.
Author_Institution
Electr. & Comput., Eng. Dept., Univ. of Patras, Patras, Greece
fYear
2011
fDate
6-8 July 2011
Firstpage
1
Lastpage
6
Abstract
This work improves the performance of LDPC decoders that implement iterative algorithms dominated by oscillatory behavior - such as offset Min-Sum algorithm - in cases of unsuccessful decoding of received words. The proposed LDPC decoder is applied on the decoding procedure of an LDPC algorithm by selecting the one of the N different estimated codewords (each produced at an iteration of the decoder) that corresponds to the syndrome with the minimum number of unsatisfied check constraints, as the output of the decoder. This method provides a decoder that achieves a notable performance improvement in the error floor region of operation for the offset Min-Sum decoding algorithm, with an insignificant increase of the hardware complexity.
Keywords
iterative decoding; parity check codes; error floor region; hardware complexity; iterative algorithms; offset min-sum decoding algorithm; oscillatory behavior; syndrome-based LDPC decoder; Bit error rate; Decoding; Hardware; Iterative decoding; Measurement; Throughput; LDPC decoding; error-floor; low BER; message-passing; oscillation; syndrome;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Signal Processing (DSP), 2011 17th International Conference on
Conference_Location
Corfu
ISSN
Pending
Print_ISBN
978-1-4577-0273-0
Type
conf
DOI
10.1109/ICDSP.2011.6004950
Filename
6004950
Link To Document