Using functional information and strategy switching in sequential ATPG

Automatic test pattern generation (ATPG) requires justification of logic values on internal lines of circuits. For sequential circuits, the justification backtraces to primary inputs or flip-flops. Primary input values may be specified arbitrarily. In contrast, the required logic values at flip-flops must be justified backward through multiple time frames, and this often produces logic conflicts which cause backtracks. We employ functional analysis of the sequential circuit so as to minimize the number of logic value assignments to flip-flops. We also present strategy switching between two efficient state justification methods. Mutually complementary properties of the two state justification methods turn out to be very effective. These refinements significantly improve ATPG performance for sequential circuits