• DocumentCode
    3083330
  • Title

    Distortion-free stacked CMOS image sensor with 8.6-μm pitch micro-bump interconnections

  • Author

    Ishizuka, Shuhei ; Takemoto, Y. ; Kobayashi, Kaoru ; Tsukimura, M. ; Takazawa, N. ; Kato, Haruhisa ; Aoki, J. ; Saito, Hiroshi ; Kondo, Toshiaki ; Gomi, Y. ; Matsuda, Shodai ; Tadaki, Y.

  • Author_Institution
    Olympus Corp., Tokyo, Japan
  • fYear
    2013
  • fDate
    12-15 Dec. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A distortion-free stacked CMOS image sensor with high density micro-bump interconnections was developed. This sensor consists of a photodiode substrate and storage node substrate and was fabricated with a wafer-on-wafer stacking technology. More than 90,000 micro-bump interconnections at a pitch of 8.6 μm per chip convey the signals. A distortion-free image was successfully obtained with the developed sensor. A parasitic light sensitivity of -160 dB was achieved by means of a light shield that uses the three-dimensional structure. It was confirmed that the stacking process caused no harm to the CMOS image sensor characteristics. A connection yield of over 99.9 % and reliable connections for practical applications were achieved.
  • Keywords
    CMOS image sensors; integrated circuit interconnections; distortion-free stacked CMOS image sensor; high density microbump interconnections; light shield; parasitic light sensitivity; photodiode substrate; storage node substrate; three-dimensional structure; wafer-on-wafer stacking technology; Arrays; CMOS image sensors; Integrated circuit interconnections; Photodiodes; Stacking; Substrates; 3D integration; bump; global shutter; image sensor; stacked;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE
  • Conference_Location
    Nara
  • Print_ISBN
    978-1-4799-2313-7
  • Type

    conf

  • DOI
    10.1109/EDAPS.2013.6724442
  • Filename
    6724442