Title :
A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2
Author :
Greenley, B.R. ; Moon, Uiz-Ku ; Veith, Raymond
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Abstract :
This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R architecture is used. The DAC was designed in a standard digital 0.18 μm CMOS process. The DAC occupies 0.0143 mm2 (110 μm×130 μm), and consumes 2.8 mW of power. The 5 stage cascaded op-amp with feedforward compensation achieves 130 dB of gain with 81° phase margin while consuming only 60 μW
Keywords :
CMOS integrated circuits; compensation; digital-analogue conversion; feedforward; mixed analogue-digital integrated circuits; operational amplifiers; 0.18 micron; 1.8 V; 10 bit; 130 dB; 2.8 mW; 60 muW; CMOS DAC cell; circuit calibration techniques; digital-to-analog converter; feedforward compensation; five stage cascaded op-amp; mixed signal ASICs; segmented plus binary plus R-2R architecture; standard digital CMOS process; ultra high gain op-amp; CMOS process; Calibration; Circuits; Design engineering; Feedforward systems; Low voltage; Moon; Operational amplifiers; Performance gain; Resistors;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921880
